1. Field of the Invention
The present invention relates to a static random access memory (SRAM), and more specifically, to an SRAM in which a silicide interface is utilized to separate a load and a connector.
2. Description of Related Art
The SRAM has the highest operating rate of all memory devices. Therefore it is applicable in many fields such as cache memory for data processing. For example, in a digital device such as a minicomputer or microprocessor, the role of the SRAM has been recognized.
Referring to FIG. 1, a typical SRAM memory unit 10 includes two resistors (or loads) R1 and R2, and four MOS transistors T1, T2, T3 and T4. The resistor R1 and MOS transistor T1 constitute a series circuit 10a in which the two terminals are connected to a voltage source Vcc and grounded to Vss, respectively. Similarly, the resistor R2 and transistor T2 form a series circuit 10b which is connected between the voltage source Vcc and ground Vss. The series circuits and the voltage sources are connected through semiconductor process, thereby forming the memory cell 10.
Moreover, gate G2 of the transistor T2, drain D1 of transistors T1 and drain D3 of transistor T3 are connected at node A. The gate G1 of transistor T1, drain D2 of transistor T2 and drain D4 of transistor T4 are connected at node B. Gate G3 of transistor T3 and gate G4 of transistor T4 are connected together to a word line WL. Source S3 of transistor T3 and source S4 of transistor T4 are connected to a bit line BL and a complementary bit line BL. The transistors can be enhanced-mode NMOS transistors, wherein transistors T1 and T2 are provided for drivers, and transistors T3 and T4 are transfer transistors. The resistors R1 and R2 are loads for reducing leakage currents at nodes A and B.
Since the aforementioned memory unit requires four transistors, the integrity is lower than with other memory devices. Especially when a sub-micron technology is applied, the SRAM process always encounters the problem of insufficient margin. The large area occupied by the loads (R1, R2) is a principle reason.
FIG. 2A through 2D are cross-sectional views of the SRAM memory unit 10. Referring to FIG. 2A, a P-well is formed in a semiconductor substrate 100 for fabricating the transistor T1 thereon. The transistor T1, which is formed by a conventional method, includes a polysilicon gate 13 (G1), a gate insulating layer 10 and a dielectric spacer 18 on sidewall of the gate. Referring to FIG. 2B, an insulating layer 22 is formed over the transistor T1. The insulating layer 22 is defined to form a dielectric window 23 in which a portion of the gate 13 is exposed. The substrate and the dielectric window 23 are then covered by a polysilicon layer 24, which is implanted with N impurities, and is patterned as a load.
Referring to FIG. 2C, a photoresist layer 26 is formed over the polysilicon layer 24 and is patterned to define the region of the load. The region covered by the photoresist layer 26 is a lightly-doped load 24a. Other regions of the polysilicon layer 24 uncovered by the photoresist layer 26 are then implanted with N+ ions to be connectors 24b and 24c. The photoresist layer 26 is removed after the ion implantation step, thereby producing the structure of FIG. 2D.
Referring to FIG. 2D and FIG. 1, load 24a (R2) has an end 210 electrically connected to gate 13 (G1) of transistor T1 and N-type lightly-doped drain D1 of transistor T2 through connector 24b, which is equivalent to node B of FIG. 1. The other end of the load 24a (R2) is connected to voltage source Vcc through connector 24c.
However, referring to FIG. 3A and FIG. 3B, since the load 24a and connectors 24b and 24c are formed by implanting ions of different concentrations therein, lateral diffusion will happen at joints 210 and 220 of the connectors 24b, 24c and the load 24a when the thermal cycling of back-end processes is carried out. For example, referring to FIG. 3B, the heavily-doped connectors 24b and 24c are expanded to 24b' and 24c', thereby reducing the length L of the load 24a to L'. The shortened load 24a' may easily induce punch-through. Therefore, the dimension of the SRAM cannot be decreased or the performance of the SRAM may be affected.